1. Field of the Invention
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including advanced transistor elements that comprise complex gate electrode structures including a sophisticated gate dielectric, such as a high-k gate dielectric, and a metal-containing electrode material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, which in turn causes an increase of gate resistivity due to the reduced dimensions, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations produced by volume production techniques. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material for a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon and metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a very pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required high capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, the usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical circuit portions, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for performance driven circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, various measures have been proposed for increasing the dielectric strength and the effective dielectric constant of the silicon dioxide material, such as performing treatments on the basis of nitrogen in order in incorporate a certain amount of nitrogen. Although these treatments of the base oxide material provide significant improvements, further scaling of the transistor dimensions may demand even further sophisticated approaches. To this end, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide based layer. It has thus been suggested to replace at least a portion of the conventional silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides an increased capacitance based on the same or greater thickness as a silicon dioxide based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone.
Since the threshold voltage of sophisticated transistor elements strongly depends on the work function of the gate electrode material, which in turn is significantly determined by the characteristics of the dielectric gate material, an appropriate adaptation of the electronic characteristics may typically have to be performed in order to obtain the desired work function values for P-channel transistors and N-channel transistors, respectively. For this purpose, typically, appropriate metal species may be provided in the vicinity of the gate dielectric material and may be diffused towards and into the gate dielectric material at any appropriate manufacturing stage so as to obtain a desired value of the resulting work function. Consequently, different metal species may be required to be positioned in the vicinity of the gate dielectric material, which may generally result in a very complex manufacturing sequence. For example, in some conventional approaches, the adjustment of the work function and the formation of the actual electrode material is accomplished in an early manufacturing stage, that is, upon patterning the gate electrode structure, which may result in a very complex gate layer stack, since a plurality of diffusion and cap layers may have to be provided in a different composition in the gate electrodes of P-channel transistors and N-channel transistors, and the required diffusion may be initiated during the high temperature anneal processes that are typically applied upon activating the dopants in the drain and source regions and re-crystallizing implantation-induced damage. In other conventional approaches, the manufacturing process may be performed on the basis of a significantly less complex gate layer stack by omitting any diffusion and cap layers in the gate electrode, thereby providing a substantially uniform process sequence with respect to N-channel transistors and P-channel transistors, wherein, however, in a very advanced manufacturing stage, the corresponding placeholder materials, such as polysilicon, have to be removed and replaced by appropriate work function metals and electrode metals, which are different for the P-channel transistors and N-channel transistors, thereby also requiring a very complex process sequence in an advanced manufacturing stage. Consequently, omitting the diffusion layers and cap layers at an early manufacturing stage, i.e., after providing the high-k dielectric material, in a so-called replacement gate approach is associated with a very complex process sequence in a very advanced manufacturing stage, while significant irregularities and thus transistor variabilities may also be introduced during the process sequence for exposing the placeholder material, removing the same and forming different types of work function metals and metal-containing electrode materials. On the other hand, adjusting the work function at an early manufacturing stage may result in a very complex and different structure of the gate electrodes, as will be explained with reference to FIG. 1
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, above which is formed a semiconductor layer 102 in which a first active region 102A and a second active region 102B are provided, for instance, delineated by an isolation structure (not shown). Typically, the semiconductor layer 102 represents a silicon material which, in the manufacturing stage shown, may comprise appropriate dopant species in order to define the basic transistor characteristics, such as conductivity type and the like. Furthermore, the first active region 102A, which represents a P-channel transistor, may additionally comprise, at least partially, above the basic active region 102A, a threshold adjusting semiconductor alloy 102D, for instance in the form of a silicon/germanium material, in order to provide an additional valence band offset to obtain a desired threshold in combination with the work function to be adjusted for a gate electrode structure 135A. The gate electrode structure 135A comprises a gate dielectric material 110, which may comprise a “conventional” gate dielectric material 111 in the form of a silicon oxide based material, such as a silicon oxynitride and the like, followed by a high-k dielectric material 112, such as hafnium oxide, hafnium silicon oxide and the like, as is also explained above. Moreover, the gate electrode structure 135A comprises a plurality of cap and diffusion layers, such as a titanium nitride layer 122 and a diffusion layer 123, which may comprise an appropriate metal species, such as aluminum, followed by a further cap layer, i.e., a titanium nitride layer 121. Additionally, a further diffusion layer 126, such as a lanthanum layer, is provided in combination with a titanium nitride cap layer 127, wherein the layers 126, 127 may represent materials as are required for a gate electrode structure 135B of an N-channel transistor to be formed in and above the second active region 102B. Finally, the gate electrode structure 135A may comprise an amorphous or polycrystalline silicon material 114 and 115, depending on the overall process strategy. Similarly, the gate electrode structure 135B may comprise the gate dielectric materials 111 and 112 followed by the diffusion layer 126, i.e., the lanthanum layer, in combination with the titanium nitride layer 127 followed by the silicon layers 114 and 115. Consequently, due to the plurality of cap layers and diffusion layers, the gate electrode structures 135A, 135B may have a very different configuration caused by the preceding manufacturing process. That is, typically, the gate dielectric material 110 is provided by oxidation and deposition techniques in combination with any other appropriate surface treatments and the like, followed by the deposition of a layer system comprising the layers 123, 122 and 121, which is subsequently selectively removed from above the second active region 102B by providing an etch mask and removing the materials selectively with respect to a gate dielectric material 110. Thereafter, the layers 126 and 127 are deposited, followed by the deposition of the silicon materials 114 and 115. Thereafter, a very complex patterning sequence has to be performed on the basis of sophisticated lithography and etch techniques, wherein the gate electrode structures 135A, 135B may differ in height and configuration, thereby contributing to process and device variabilities. For example, in semiconductor devices with a gate length, i.e., in FIG. 1 the horizontal extension of the gate electrode structures 135A, 135B, of 40 nm and less, material residues may be observed at the foot of the gate electrode structure 135A, while the structure 135B may suffer from additional undercut, depending on the corresponding process treatments. Hence, upon continuing the further manufacturing process for completing the transistors in and above the active regions 102A, 102B, even further increased process-related irregularities may be introduced. Finally, after forming drain and source regions, the subsequent annealing process may result in a diffusion of metal species of the layer 123 towards the gate dielectric material 110 via the cap layer 123 in order to obtain the desired work function, while, in the gate electrode structure 135B, the lanthanum species in the layer 126 may diffuse into the dielectric material 110.
Although the manufacturing strategy described with reference to FIG. 1 may principally result in sophisticated transistor elements, it turns out that, in volume production, the process-related irregularities may contribute to a significant yield loss, thereby making this approach less than desirable.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.